Search results for "Time-to-digital converter"
showing 8 items of 8 documents
A compact system for high precision time measurements ( < 14 ps RMS) and integrated data acquisition for a large number of channels
2011
A high precision ( < 14 ps RMS time resolution) and high channel density ( ~ 256 channels) Time to Digital Converter (TDC) module (realized in FPGAs) with integrated DAQ is presented. The data is transported over up to 8 Gigabit-Ethernet or optical links with up to 3 Gb/s. Slow-Control information is transported over the same links. It can be attached directly to the detector, which allows the elimination of long cables and crate systems. The full 256 channel TDCs are expected to use approximately 30 W electrical power. The module size is 20 cm by 23 cm. Power is provided by a galvanically isolated 48 V low noise power supply. AddOn-boards adapt to the special needs of the detector to be re…
Timing results using an FPGA-based TDC with large arrays of 144 SiPMs
2015
Silicon photomultipliers (SiPMs) have become an alternative to traditional tubes due to several features. However, their implementation to form large arrays is still a challenge especially due to their relatively high intrinsic noise, depending on the chosen readout. In this contribution, two modules composed of SiPMs with an area of roughly mm mm are used in coincidence. Coincidence resolving time (CRT) results with a field-programmable gate array, in combination with a time to digital converter, are shown as a function of both the sensor bias voltage and the digitizer threshold. The dependence of the CRT on the sensor matrix temperature, the amount of SiPM active area and the crystal type…
A 16 channel high resolution (<11 ps RMS) Time-to-Digital Converter in a Field Programmable Gate Array
2012
A 16-channel Time-to-Digital Converter (TDC) was implemented in a general purpose Field-Programmable Gate Array (FPGA). The fine time calculations are achieved by using the dedicated carry-chain lines. The coarse counter defines the coarse time stamp. In order to overcome the negative effects of temperature and power supply dependency bin-by-bin calibration is applied. The time interval measurements are done using 2 channels. The time resolution of channels are calculated for 1 clock cycle and a minimum of 10.3 ps RMS on two channels, yielding 7.3 ps RMS (10.3 ps/√2) on a single channel is achieved.
High Resolution Time Domain Reflectometry for Dielectric State Monitoring in High Voltage Cables
2017
A high resolution Time Domain Reflectometry system has been designed in order to investigate the possibility of measuring with good accuracy the dielectric properties of high voltage cables insulator materials by means of Time-of-Flight measures. The system employs a dedicated Time-To-Digital Converter in order to achieve a time resolution of 90 ps. By exploiting averaging techniques the resolution has been further increased. Experimental results showed the possibility of measuring the dielectric constant with a resolution of 0.03%.
Frontend electronics for high-precision single photo-electron timing using FPGA-TDCs
2014
Abstract The next generation of high-luminosity experiments requires excellent particle identification detectors which calls for Imaging Cherenkov counters with fast electronics to cope with the expected hit rates. A Barrel DIRC will be used in the central region of the Target Spectrometer of the planned PANDA experiment at FAIR. A single photo-electron timing resolution of better than 100 ps is required by the Barrel DIRC to disentangle the complicated patterns created on the image plane. R&D studies have been performed to provide a design based on the TRB3 readout using FPGA-TDCs with a precision better than 20 ps RMS and custom frontend electronics with high-bandwidth pre-amplifiers and …
Time of flight measurements based on FPGA and SiPMs for PET–MR
2014
Coincidence time measurements with SiPMs have shown to be suitable for PET/MR systems. The present study is based on 3 x 3 mm(2) SiPMs, LSO crystals and a conditioning signal electronic circuit. A Constant Fraction Discriminator (CFD) is used to digitalize the signals and a TDC FPGA-implemented is employed for fine time measurements. TDC capability allows processing the arrival of multiple events simultaneously, measuring times under 100 ps. The complete set-up for time measurements results on a resolution of 892 +/- 41 ps for a pair of detectors. The details of such implementation are exposed and the trade-offs of each configuration are discussed. (C) 2013 Elsevier By, All rights reserved,
Optimization of a Time-to-Digital Converter and a coincidence map algorithm for TOF-PET applications
2015
This contribution describes the optimization of a multichannel high resolution Time-to-Digital Converter (TDC) in a Field-Programmable Gate Array (FPGA) initially capable of obtaining time resolutions below 100ps for multiple channels. Due to its fast propagation capability it has taken advantage of the FPGA internal carry logic for accurate time measurements. Furthermore, the implementation of the TDC has been performed in different clock regions and tested with different frequencies as well, achieving improvements of up to 50% for a pair of channels. Moreover, since the TDC is potentially going to be used in a trigger system for Positron Emission Tomography (PET), the algorithm for coinci…
High-resolution multichannel Time-to-Digital Converter core implemented in FPGA for ToF measurements in SiPM-PET
2013
In this contribution, Coincidence Resolving Time (CRT) results with the developed multichannel FPGA-TDC are showed as a function of different configurations for both, the sensor bias voltage and the digitizer threshold. The dependence of the CRT with the sensor matrix temperature, the amount of SiPM active area and the crystal type are also analyzed. Preliminary measurements carried out with a crystal array of 2 mm pixel size and 10 mm height have shown time resolutions for the entire 144 SiPM two-detectors ensemble as good as 800 ps.